There exists a variety of digital data systems, including but not limited to multiple access communication systems, wherein it is necessary or desirable to transfer data which is generated in the domain of one clock frequency to the domain of another clock frequency. Such a requirement may arise because the first domain includes or is controlled by a microprocessor operating at a particular design frequency and the system operating in that domain must be interfaced with a second system which by design or convention operates at a different clock frequency. Systems for changing from one clock frequency domain to another are known in various forms. Where latency, that is to say the time of propagation of a given signal through a system, is not of prime concern within quite wide limits, it has been customary to employ storage buffers into which data is clocked at a first frequency and is read out at a second clock frequency. Systems of this nature are not satisfactory in particular in high speed communication systems where information flow is very substantial, making the use of buffers undesirable, and where any latency which is more than a minimum is likewise undesirable.
It is possible to provide a system comprising a bistable register which receives data, such as decoded address data, and is clocked by a first clock signal to a state machine which couples data out to a bistable register operating at a second clock frequency, but such schemes do not provide a transfer of data from one clock domain to another with minimum latency and a guarantee of stability.
It is the general object of the present invention therefore to provide an improved method or technique for the transfer of data from one domain to another. It is a further object of the invention to provide a fairly simple circuit arrangement, i.e. hardware, for achieving such a transfer.